Many computer applications benefit from driving multiple display monitors from a single computer system. Such multiple monitor systems achieve greater display capability without the expense or inconvenience of a single, larger monitor. Consumers have demanded multi-monitor systems to more fully exploit the abilities of improved processors and the multi-tasking efficiency of new operating systems. Additionally, multi-monitor systems allow for enlarged display area as desired by professionals in the CAD, video editing, financial, and controls fields where multiple system components and parameters may have to be simultaneously monitored.
Implementing a multi-monitor computer system has been problematic because of preexisting industry standards developed in the single monitor display environment, in particular, the VGA display standard and the Peripheral Component Interconnect ("PCI") bus standard. Generally, a multi-monitor display system includes two or more monitors each driven by a graphics chip, a central processing unit ("CPU"), and a data bus for use in exchanging information between the CPU and the monitors/graphics chips. The VGA standard, which is implemented in many commercial graphics chips, was developed in the context of so-called legacy devices. Legacy devices are characterized in that they utilize their own unique resources such as memory address space, input/output ("I/O") address space, interrupt request lines and direct memory access ("DMA") channels. In this regard, VGA compatible graphics cards are mapped to predefined or dedicated resource spaces. For example, memory space may be mapped to hex addresses in the range a0000-dfff depending on the VGA mode and I/O space may be mapped to 3c0-3cf and either 3b4/3b5/3ba or 3d4/3d5/3da depending on the VGA mode. These mappings/resource usages are fixed per the VGA specification and cannot be changed.
Most commercially available graphics chips include a VGA compliant mode of operation. Such chips persist for a number of reasons including the continuing availability and use of VGA related devices and software written with the expectation that given legacy devices will use predefined resources. The VGA chips thus provide VGA compatibility for computer boot purposes, but may also implement extended non-VGA registers for various high-end features. These chips are nonetheless VGA compatible and are considered VGA devices.
Legacy devices may be contrasted with emerging non-legacy or so-called plug and play ("PNP") devices. PNP devices are characterized by the ability to be configured so as to utilize available resources. That is, PNP devices do not require predefined, dedicated address space for various resources. PNP technology involves a hardware implementation and related software or logic support. The hardware implementation allows PNP devices to have resource settings set electronically, i.e., without user set jumpers or switches. In addition, PNP hardware devices boot (start) in an unconfigured, turned off state. PNP software or logic support involves examining the system, determining what resources are available (not in use by another device), determining what resources the PNP hardware needs by querying the PNP hardware, setting up the PNP hardware to use those available resources and then turning on the PNP hardware.
The PCI bus standard is designed to accommodate PNP devices. To that end, the PCI specification provides for software driven initialization and configuration of PNP peripheral devices such as PCI cards. Generally, under the PCI protocol, the computer Basic Input/Output System (BIOS) scans the PCI bus, when the system is first turned on, to determine what resources each PCI device needs. The BIOS then assigns non-conflicting resources to each card, turns each card on, and initializes each card that may include an initialization routine in a card BIOS (VGA devices will include such a routine). Note that this initialization procedure may be repeated at a later time, for example, when a graphical user interface (GUI) operating system boots.
A problem arises when more than one legacy device of a particular type is implemented in a PCI system. The problem stems from the fact that legacy devices demand dedicated resources. Two legacy devices of the same type may therefore require access to the same memory space. Thus, upon initialization, if the system BIOS assigns the required resources to a first legacy device, the resources will be unavailable for the second legacy device. As a result, the system BIOS would be unable to turn on and initialize the second legacy device according to a conventional PCI resource allocation cycle. Software cannot use these legacy devices while they are turned off and not initialized.
A solution to the above-described problems is described in U.S. Pat. No. 5,848,294 for PCI COMPUTER SYSTEM WITH MULTIPLE LEGACY DEVICES, which is assigned to the assignee of this application and is incorporated herein by reference. The control subsystem described therein is implemented as software that alternately provides access to the system CPU by each of the monitors on an exclusive basis and at separate times on an as-needed basis. By virtue of the independence of the control subsystem from the monitors, VGA monitors can be run in a manner that mimics plug and play functionality, and the control subsystem can be made compatible with multiple legacy device types.
However, because the multiple monitors are driven from separate VGA chips that are, in turn, controlled by software operations occurring at unpredictable times, the monitors are typically not synchronized. That is, the vertical and/or horizontal sync signals driving the monitors do not occur at the same instants in time. Unfortunately, placing two or more unsynchronized monitors in close proximity to each other may cause their electromagnetic fields to interfere with each other, causing undesirable horizontal or vertical shading bars on at least one of the monitors. The conventional way of synchronizing monitors is by employing a commonly clocked, or hardwired, synchronization clock for all of the monitors. However, such a solution is not readily implemented in the above-described multiple display chip, multiple monitor configuration, and the problem is not limited to legacy monitor configurations.